1. Field of the Invention
The present invention relates to the field of analyzing the operational behavior of digital circuits at least partially in real time or approximately in real time by using a hardware implementation of the circuit design, such as a semiconductor chip including the circuit design, a prototype version, a field programmable gate array, and the like.
2. Description of the Related Art
The manufacturing of new types of digital integrated circuits or integrated circuits including a digital circuit portion typically requires a thorough verification of the functionality of the circuit design prior to the actual mass production process. That is, the behavior of the circuit has to match the desired functionality for any specified operating conditions. Due to the immense costs of the fabrication process of only a few integrated circuits, the circuit verification is often performed prior to actually manufacturing prototype versions in silicon. One approach in this respect is the conversion of the digital circuit design into a corresponding design model to simulate the operation of the circuit by software. For moderately complex circuit designs, however, the simulation requires great efforts in terms of time and processor resources and may take several weeks to several months. Thus, the simulation time may contribute approximately 60-80% to the total development time of a project. Consequently, the software simulation of the digital circuit design, although providing 100% design visibility, i.e., offering the potential for observing the complete status of the circuit at any time, is a less attractive approach in view of the extended time period from designing to actually producing a specified digital circuit design.
For this reason, attempts have been made to accelerate the circuit verification phase by providing hardware components representing the circuit design or portions thereof in combination with a software simulation, wherein an increased amount of hardware used in a DUT (device under test) may significantly reduce the requirements with respect to the software resources for simulating the circuit design, thereby also, however, reducing the degree of design visibility. For instance, the circuit design under consideration may be implemented, entirely or in part, by programmable logic devices (PLDs), such as field-programmable gate arrays (FPGAs), which allow, depending on the capability of the PLD used, an operation of the DUT at the speed, or nearly at the design speed, for which the integrated circuit is intended to be operated after the production. A hardware representation of the circuit design or a portion thereof by means of a programmable logic device enables, contrary to manufacturing a test silicon chip, a fast implementation and opens the possibility for re-designs of the circuit design, if necessary, by correspondingly re-configuring the programmable logic device. Moreover, running the hardware representation in a target system provides enhanced design verification capabilities and also supports the software development for the target system, wherein a mutual adaptation of the software for the target system and the hardware representation may readily be achieved by appropriately re-programming the software and the programmable logic device. Despite these advantages, the substantially hardware-based circuit design verification comes along with an extremely reduced design visibility compared to the software simulation of the circuit design, thereby also drastically reducing the debug capabilities, i.e., the capability of identifying and remedying errors in the circuit design.
While the software simulation, providing enhanced design visibility and thus debug capabilities, requires extended periods of simulating the circuit design under consideration, the hardware or prototype based verification, providing enhanced operation speed of the DUT and thus a high degree of similarity to actual operating conditions in a target system, renders debugging, i.e., identifying the root cause of any invalid behavior, difficult.
In view of the above-explained situation, a need exists for an improved technique of verifying a digital circuit design in a timely and cost-efficient manner while still providing a high degree of design visibility during the test phase.